About me

2024-Present

AMD

San Jose, California, USA

Debug and Diagnosis Team, Senior Member of Technical Staff

Experienced in silicon debug and DFT methodologies, focusing on pattern generation, validation, and failure analysis across ATE and custom platforms. Worked on HBM3 failure research and DFT improvements for MI300X, with close collaboration across DFX teams to enhance testability and debuggability

2022-2024

Qualcomm

San Diego, California, USA

Yield and Diagnosis Team, Senior Engineer

Focused on MBIST test and diagnosis, including verification methodology development and on-chip memory diagnostics. Contributions to burn-in screening, SPC/WS data analysis, and defect prediction systems in collaboration with the foundry.

2020-2022

Samsung Foundry

Hwaseong-si, South Korea

DFT Team, Staff Engineer

Experienced in DFT and ATPG for advanced nodes, including 3nm GAA-based mass production and customer product support.

Developed logic diagnosis methodology including cell-aware and layout-aware techniques, and drove volume diagnosis innovation for systematic defect detection using machine learning

2014-2020

Yonsei University

Seoul, South Korea

Ph.D and Master degree in Electrical and Electronic Engineering

Thesis: Effective DRAM-based On-Chip Error Detection Methodology for Post-Silicon Debug

Lead MPW team for reliable Near Threshold Voltage aware processor

Participated with 7 projects sponsored by the Korean Government (Total project fund amount: $6M)

2007-2014

Yonsei University

Seoul, South Korea

Bachelor’s degree in Electrical and Electronic Engineering

Thesis: Effective DFT Methodology for 3D IC

GPA: 3.0/4.5